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INTRODUCTION TO SHOCC


"Seamless High Off-Chip connectivity (SHOCC) is a combined packaging, interconnect, and IC design philosophy and associated enabling technology that aims to shift the device fabrication paradigm from today's single die approach to a parallel manufacturing scheme that utilizes yield-optimized IC elements packaged using a high-performance interconnect element" [1].

The main idea behind the concept is that the interconnects on the chip in a one die system is divided between on chip and off chip interconnects. This eliminates the possibility of having long lossy transmission lines on the chip. Also, as designers are hard pressed to reduce the size of the chip, the area of the interconnects on the chips are bound to be decreased resulting in an increase in the resistance of the interconnects.

Also the number of inputs/outputs that the chip can handle can improve drastically considering that I/O can be done using the solder-pads on the chip that are distributed all over the area of the chip (in a multi-chip module) as compared to a single die where all the inputs/outputs have to be brought on the perimeter of the chip.

The SHOCC interconnects are modeled as lossy transmission line elements. This is done so that the designer can obtain accurate chip-chip delay and cross-talk noise estimates when evaluating the performance of the chip. This specially gains importance when the rise time of the signals reduces as compared to the flight time of the signal through the chip.

The design kit was to be developed within the Cadence IC environment to permit co-design and analysis of SHOCC designed chips and substrates. The new technology files and the rules files would be developed by using the SKILL programming language within the cadence environment as would be the extraction process that would permit the co-extraction of the on-chip parasitics into a high fidelity HSPICE file.
 
 

PAST WORK

A lot of work that proved to be the foundation to this project was done when researchers at NC State University developed the NCSU CDK. The Cadence Design Kit was put together to support the scalable MOSIS rule-set for IC design within Cadence. The kit and the associated flow tool were developed while research students worked on their research projects. The following section discusses the CDK.
 

The NCSU Cadence Design KIT (NCSU CDK)

The NCSU CDK is used in teaching and research purposes at NC State University and various other universities. The Cadence Design Kit has been customized with several technology files and a fair amount of skill code. These files contain information useful for full-custom CMOS IC design via MOSIS. The CDK has been used to design and fabricate working chips. The kit, which can be downloaded freely off the Internet from http://www.ece.ncsu.edu/cadence/CDK.html, contains

· Technology files and technology libraries. - These files define the masks that are available in different processes as well as the layer available. They also define the value of the lambda for that specific technology.
· Diva Rules files. - These files are specifically written for verification.

    · The Design Rule Check (DRC) checks the dimensions, distances and the validity of the geometry of the structures that are built using the  layout editor. All rules from the MOSIS SCMOS User's manual are checked. All rules are a function of Lambda - which is different for each process. The value of lambda for each process is stored in the file globaldata.il.

    · The Extraction File extracts FETs, vertical NPNs PN/NP diodes, poly-metal1/ thin-ox/poly-cap capacitors and parasitic capacitors

    · Layout Vs Schematic (LVS) files compares the netlist from the schematic that a designer draws with the netlist that Analog Artist (used for circuit simulation) generates from the layout.

    · Standard Parts Libraries. The standard parts libraries contain common analog and digital parts symbols, Verilog primitives and example sheet borders. A few more complex but commonly used parts such as the multiplexor and the flip-flops are also included in the standard parts libraries.

    · Device Models contains the transistor model files that are obtainable from the MOSIS website.


Reference:

[1]  Seamless High Off-Chip Connectivity
        L. Schaper, M. Dibbs, P. Garrou, C.C. Chau, Y. So, D. Frye, J. Wagner, J. Ousley, G. Baugher, R. Picard, G. Connor, D. Winn, P. Deane, R. Eden, and R. Sands
        IEEE Symposium on IC/Package Design Integration February 2-3, 1998  Santa Cruz, California.

[2]  COMPUTER AIDED TOOLS FOR SEAMLESS HIGH DENSITY INTERCONNECTS
        Ambrish K Varma
        Master's Thesis, North Carolina State University, April 2001.